Saving computing power with the right choice of sampling time

When designing an embedded system that interacts with its physical environment, the choice of sampling time is essential. It has an influence on the quality and attainability of the control tasks, but also on the required computing power.

In a nutshell, a shorter sampling time leads to better controller performance but also requires more computing power. Building on that, the goal is clear: Select a sampling time that is only as fast as necessary.

But how fast is that?
To provide our customers with a cost-efficient product that meets all technical requirements, it is important to be able to answer this question.

1. Rules of thumb for selecting sampling time

For the choice of the sampling time there are a vast number of different rules of thumb. What they all have in common is that they always refer in one way or another to the desired speed of the closed control loop. The parameters which are used for this, among others, are:

• \( t_r \) Rise time
• \( t_s \) Settling time
• \( \omega_c \) Cross-over frequency)
• \( T_i \) Time constant)

 

In addition, the procedure used for the controller design has an influence. If the controller is designed in the continuous time domain and then transformed into the discrete time domain, this simplifies the design process, but requires somewhat faster sampling times to deliver good controller performance. This is mainly because the approximation of the continuous controller improves with shorter sampling times.

If the controller design is done directly in discrete time space, the sampling time can be chosen somewhat larger, since the controller performance does not depend on the accuracy of an approximation.

Perhaps we increase the number of existing rules of thumb by the following two, but in the first place it is only about getting a feeling for a reasonable range of the sampling time . The most intuitive parameter is probably the desired rise time, in combination with the “nice” numerical values this results in a quite memorable rule.

Approximation of an equivalent digital controller:

\( \frac{t_r}{5}\geq T\geq\frac{t_r}{100} \)

Direct digital designed controller:

\( \frac{t_r}{2}\geq T\geq\frac{t_r}{100} \)

 

In the following chapters, an example is used to explain the factors that lead to chosen limits.

 

2. Reglerperformance in Abhängigkeit von der gewählten Abtastzeit

To investigate the influence of the selected sampling time T on the performance of the control, for a PT1 path of the form:

\( P\left(s\right)=\ \frac{1}{s+1} \)

 

The controller shall reduce the rise time of the system from about 3 seconds to about 1 second. To achieve this, we use a continuous controller of the form:

\( C\left(s\right)=1+\frac{1}{0.5\ s} \)

 

For the approximation of an equivalent digital controller, we use the bilinear transformation (also called Tustin’s method). This yields a controller of the form:

\( C_{ed}\left(z\right)=2\ \bullet\frac{z}{z-1} \)

 

The directly digitally designed controller is selected so that the poles of the closed loop are at the same position as the poles of the continuous closed loop after a ‘sample and hold’ element. This way, we try to approximate the step response of the continuous system. Here it is already apparent that this type of design is more complex as each selected sampling time results in a new controller, for which the parameters depend on the sampling time.

\( C_{dd}\left(z\right)=\ \kappa(T)\bullet\frac{z-\beta(T)}{z-\alpha(T)} \)

 

Figure 1 shows the step responses for sampling times T =1 to T = 0.01 in animated form.

For both design methods, it is easy to see that the shorter the sampling time, the closer they come to the continuous target. Good results are already obtained for \( \frac{t_r}{2} \) = 0.5 (direct digital design) resp. \( \frac{t_r}{5} \) = 0.2 (digital approximation).

 

Is it possible to go even slower?

The crossing frequency of the closed loop for our example is \( \omega_c \) = 1.41. The Nyquist frequency is \( \omega_N=\frac{\pi}{T} \), so to satisfy the Nyquist criterion the sampling time must be less than 2.23 s. What such high sampling times mean for the controller performance can be seen in Figure 2. For very high sampling times of more than 3 s, it is easy to see that the information about the speed of the system can no longer be represented. For this example, this does not lead to instability, but with an increasing sampling time, the system approaches the uncontrolled plant.

3. Dead time through digital implementation

The above example does not consider that a real implemented digital controller always needs time to calculate the output value. The time needed to measure the input value, to perform the calculations for the control algorithm, and to output the result inevitably leads to a transport delay. If this is not considered in the design of the controller, it can lead to an unstable system, since the dead time represents a phase loss, and this directly reduces the phase margin of the controller.

In the technical implementation, there are several possibilities to deal with the delay introduced by the controller. The problem that arises is that this time does not always have to be the same and can lead to time fluctuations when applying the output values. Therefore this corresponds to a variable dead time, and as already mentioned, dead times that are not considered can lead to instabilities. To avoid this uncertainty, it is possible to write the outputs always at the next sampling time. This approach is preferred especially for safety-critical applications to minimize the associated risks. This approach was also chosen for our example and a constant dead time of the size of the sampling time T is obtained.

Figure 3 shows the step response for our example when the dead time is not considered in the controller design. The animation shows the results for sampling times from T = 1 to T = 0.01.

The result is better the shorter the sampling time. This is easy to understand since the dead time/sampling time has a direct effect on the controller performance via the phase margin.

However, if this additional dead time is considered when designing the controller, good controller performance can also be achieved here. Figure 4 shows the step responses for sampling times T = 1 to T = 0.01 in animated form.

Of course, the dead time also has an influence on the reaction to external disturbances. Figure 5 shows the reaction to a suddenly occurring constant disturbance. Again, this is animated over the sampling time from T = 1 to T = 0.01.

However, this is the ‘best-case’ case in which the disturbance occurs exactly at the time when the value is sampled. If you look at the ‘worst case’, that the disturbance occurs just after the reading of the measured value, you get the picture shown in Figure 6.

It can therefore be stated that long sampling times have a greater influence on the disturbance rejection than on the command tracking.

 

4. Numerical problems with small sampling times

One could now assume that it can generally be said for the performance: The faster the better. However, as can be seen from the title of this section, the required computing power is not the only reason for a lower limit of the sampling time in the rules of thumb defined above.

 

Why does the sampling time have an influence on numerical problems in the implementation?

This can be shown very clearly using the pole-zero diagram. Figure 7 shows the pole-zero diagram for a system with two distinctly different pole locations (s1 = 1 and s2 = 10) after discretization with different sampling times. It can be seen that with decreasing sampling time the poles move closer and closer to the unit circle and the distance decreases more and more. It is now easy to imagine that with a limited precision of the numerical representation, the two poles can no longer be kept apart.

The lower the sampling time, the higher the demand for the numerical representation of a digital controller, and since this cannot be increased arbitrarily, there is also a lower limit for the sampling time.

 

What does this mean for our example controller?

If we assume an implementation with fixed point values with 3 decimal places, this means that errors occur in the mapping of the parameters and states as well as rounding errors in the calculations. The result for the step response of the system is shown in Figure 8 for sampling times from T = 1 to T= 0.01.

The numerical behavior also depends on the chosen implementation form of the digital controller. For this example, the Direct Form I was chosen.

The basis for the selection of the sampling time is the speed of the closed control loop. There is a whole series of parameters that represent this. In this article, we proposed a rule of thumb based on the understandable parameter of the rise time. The range is between 2 and 100 samples within the desired rise time.

It has been shown that controller performance benefits from a smaller sample time. And that the influence on the disturbance rejection is even greater.

Drawbacks of too small sampling times are the increased required computing power and possible numerical problems.

In Figure 9 the rules of thumb are shown as a colored area. The two curves show a deviation measure, that is zero when the desired step response is achieved exactly and an increasing value for increasing deviations. The step response of the continuous system was used as the desired value. With high sampling times, the approximation of the controller is bad, with small sampling times numerical problems occur. It should be noted that the disturbance rejection may have to be considered as a further dimension for the selection of the sampling time.